1. Field of the Invention
The present invention relates to a ferroelectric capacitor and a semiconductor device having the same.
2. Description of the Related Art
In a semiconductor integrated circuit such as a dynamic random access memory (DRAM), a ratio of an area occupied by a capacitor in a memory cell has been increased as a capacity and a degree of integration of the IC have been increased. For this reason, a stack structure in which an electrode, a dielectric layer, and another electrode are stacked on a semiconductor substrate as a capacitor in a memory cell or a three-dimensional structure such as a trench structure in which an electrode is buried in a trench via a thin dielectric layer is adopted in, e.g., a 4-M bit DRAM. Since, however, a degree of integration is predicted to be further increased in future, it is assumed that a structure of a memory cell will be still more complicated.
For the above reasons, studies have been made to use a ferroelectric material having a high permittivity in place of an oxide or nitride of silicon which is versatilely used as a dielectric film, thereby simplifying a structure of a capacitor. For example, since the relative permittivity of lead zirconate titanate (PZT) as a typical ferroelectric material is 1,000 or more, a ferroelectric capacitor of a planar structure having the ferroelectric material can store an electric charge in a comparatively small area.
In addition, studies have been made to realize an electrically erasable nonvolatile random access memory (RAM) by using a ferroelectric capacitor. The nonvolatile RAM utilizes the fact that the ferroelectric material has hysteresis characteristics between an electric field and polarization. More specifically, the ferroelectric capacitor has relationships between an electric field E and electric polarization P as shown in FIGS. 1 and 2. FIG. 1 shows an E-P characteristic curve observed at a Curie temperature or less (ferroelectric phase), and FIG. 2 shows that observed at the Curie temperature or more (paraelectric phase). A ferroelectric capacitor having the characteristic shown in FIG. 1 holds a remanent polarization corresponding to the direction of an applied voltage even when the voltage is returned to zero. For this reason, a nonvolatile RAM having the ferroelectric capacitor is used in a state at the Curie temperature or less (ferroelectric phase) in which the capacitor exhibits the remanent polarization. The ferroelectric capacitor is allowed to store digital information by assigning the direction of an electric charge remaining in the ferroelectric material to "0" and "1". A volatile DRAM is used in a state at the Curie temperature or more (paraelectric phase) in which no remanent polarization is exhibited as shown in FIG. 2.
In addition, as is understood from the hysteresis characteristics shown in FIGS. 1 and 2, in the ferroelectric capacitor, the polarization P is no longer increased when the electric field is increased to a certain degree, i.e., a so-called polarization saturation phenomenon occurs. In the ferroelectric capacitor, therefore, even if a distance between electrodes sandwiching a ferroelectric layer is shortened, i.e., even if the thickness of the ferroelectric layer is decreased, the effect of storing a large amount of an electric charge obtained when a normal dielectric layer is used cannot be expected. On the contrary, since the dielectric strength of the ferroelectric material is comparatively low, the interelectrode distance is preferably increased to be wider than that designed when a silicon oxide or nitride is used. The interelectrode distance of the ferroelectric capacitor used in the non-volatile RAM, therefore, is preferably determined in accordance with an operation voltage, a threshold electric field (or a polarization saturation electric field) of the dielectric, a dielectric strength, and the like.
A structure shown in FIGS. 3A and 3B is known as a semiconductor device having a ferroelectric capacitor of a planar structure. Referring to FIGS. 3A and 3B, reference numeral 301 denotes a p-type silicon substrate, and a field oxide film 302 for electrically isolating an element region is formed on the surface of the substrate 301. N.sup.+ -type source and drain regions 303 and 304 are formed on the surface of the substrate 301 surrounded by the field oxide film 302 so as to be electrically isolated from each other. A gate oxide film 305 is formed on the substrate 301 including a channel region formed between the source and drain regions 303 and 304, and a gate electrode 306 consisting of, e.g., polycrystalline silicon is formed on the gate oxide film 305. A first insulating interlayer 307 consisting of, e.g., SiO.sub.2 is coated on the entire surface of the substrate 301 including the field oxide film 302 and the gate electrode 306. Contact holes 308 are formed in the insulating interlayer 307 at a position corresponding to portions of the source and drain regions 303 and 304 respectively. A source electrode (not shown) and a drain electrode 309 consisting of polycrystalline silicon are formed on the insulating interlayer 307 so as to be connected to the source and drain regions 303 and 304, respectively, through the contact hole 308. A first electrode 310a having a wide area is formed at the other end of the drain electrode 309. A second insulating interlayer 311 consisting of, e.g., SiO.sub.2 is coated on the insulating interlayer 307 including the source electrode and the drain electrode 309. A hole 312 is formed in the insulating interlayer 311 at a position corresponding to the first electrode 310a, and a ferroelectric layer 313 consisting of, e.g., PZT is buried in the hole 312. A second electrode 310b having a wide area is formed on the second insulating interlayer 311 including the ferroelectric layer 313, and a wiring 314 arranged on the second insulating interlayer 311 is connected to the second electrode 310b.
Generally, in order to increase an amount of an electric charge to be stored in the ferroelectric capacitor, an electrode area must be increased without decreasing an interelectrode distance. For example, in order to store an electric charge Q of 300 fC in a capacitor manufactured by using a ferromagnetic having a remanent polarization P.sub.R of 0.3 C/m.sup.2, the electrode area must be 1.0 .mu.m.sup.2. Since, however, the ferroelectric capacitor to be incorporated in the conventional semiconductor device shown in FIGS. 3A and 3B is of a planar structure, an increase in electrode area increases the area of a memory cell, thereby limiting a degree of micropatterning.
In addition, in the semiconductor device shown in FIGS. 3A and 3B, a low-permittivity layer is inevitably formed in an interface between the ferroelectric layer 313 and the underlying first insulating interlayer 307 when the ferroelectric layer 313 is formed by sputtering deposition or the like. For this reason, in a semiconductor device having such a ferroelectric capacitor, as shown in an equivalent circuit diagram of FIG. 4, a parasitic capacitor C' caused by the low-permittivity layer is connected in series with a ferroelectric capacitor C. As a result, total ferroelectric characteristics are degraded.
Furthermore, a certain type of a ferroelectric material has spontaneous polarization with respect to a specific crystal axis. For example, a ferroelectric layer in which the direction of a spontaneous polarization axis of a crystal corresponds to the surface direction is formed like in lead niobate. If a planar type capacitor as shown in FIGS. 3A and 3B is formed by using such a ferroelectric layer, no ferroelectric characteristics can be obtained since the direction of spontaneous polarization of the ferroelectric layer 313 does not correspond to the direction between the electrodes 310a and 310b.